The present invention relates to drive circuits for a power device of a power driving stage and particularly to a driver circuit operating from a supply voltage (e.g., a charge pump voltage) that is higher than the supply voltage of the power device. The invention is particularly beneficial for high side drivers in integrated circuits for energizing spindle motor coils, such as for hard disk drives.
A driver circuit is generally a relatively low power circuit that drives, or controls, a higher power device. The power device may be part of a power driving stage for a load. An example is a load that is a motor, such as a brushless motor, that provides the motive force for a spindle of a hard disk drive. Similar driver circuits are applied elsewhere, such as in voice coil motor (VCM) systems. One of the most widely used types of driver circuits in such applications uses a three-phase brushless motor in a configuration in which current energizes respective motor coils using a full wave bridge configuration. The bridge includes two power stages for each phase, so typically there are six power stages, each with a power device. Three of the power stages, and their power devices, are referred to as being "low side" stages and devices because they are connected between a motor coil and ground. The other three of the power stages, and their power devices, are referred to as "high side" stages and devices because they are connected between a power supply and a motor coil.
The power devices are operated as switches in a sequence that allows pulses of current to flow from the power supply through a high side power device, a coil of a first of the three stages, a coil of a second of the three stages, and then through a low side power device to ground. This process is repeated in a generally well known manner for the other power devices and coil pairs to achieve three-phase energization from a single, direct current, power supply. The switching, or commutation, characteristics of the power devices are very important in achieving good performance from the motor and other favorable characteristics.
Control of the switching of the power devices is performed by a driver circuit for each power device. In the typical use described above with six power stages, there are three low side drivers and three high side drivers. The power devices may be of a variety of electronic switch devices and the driver circuits are configured suitably for the power devices. Power devices of general application to hard disk drives, and the like, are each often an MOS (metal-oxide-semiconductor) FET (field effect transistor). One type of such transistors of considerable interest is referred to as a DMOS transistor (D referring to a double diffusion process used in its manufacture).
DMOS devices can be readily integrated in chips with other circuitry, including lower power control circuitry. So it is attractive to have an entire set of drive stages, including all the power devices and all the driver circuits for the power devices, in one chip.
Even where all the power devices are alike, e.g., N channel DMOS devices, it is generally the case that the high side drivers differ from the low side drivers because high side drivers for such power devices often require a voltage, referred to as a charge pump voltage or boost voltage at a higher voltage level than that supplied by the power supply for the power stages. By known techniques, a charge pump voltage may be generated from the supply voltage and used by all the high side drivers. Such an auxiliary supply is, however, power limited; the desired voltage can be supplied but at a modest current level.
The state of the art in the field of motion control using integrated signal and power components, the respective requirements of low and high side drivers, and the characteristics sought in applications of motor drives are described more fully in Smart Power ICs, B. Murari et al., Eds., 1995, particularly Chapter 5, "Motion Control" by R. Gariboldi, at pp. 225-283, which is herein incorporated by reference for its description of background to the present invention.
As is known, for example from the above-mentioned Gariboldi publication, for applications such as hard disk drives, it is of utmost importance to control the output voltage slope in order to reduce electromagnetic interference (EMI). Generally, the slope is desired to be steep but not so abrupt as to cause any appreciable noise. Drive circuits have therefore generally included slew rate control circuits to achieve fast, smooth transitions.
Techniques previously used for high side slew rate control (cf., Gariboldi) have included one in which the gate node of a power DMOS device is charged and discharged by constant current sources. A first constant current source is applied between the charge pump voltage supply and the gate node. A second constant current source is applied between the gate node and ground. The inherent input capacitance of the power device during rise and fall times is relatively constant. The slew rate or voltage slope is proportional to the sourced currents divided by the capacitance. Another known slew rate control technique uses a capacitor separate from the inherent capacitance of the power device. It can be more accurate since the specific capacitance used can be better controlled. However, practical limitations are encountered in order to integrate such a circuit into a small chip area.
These limitations are related to the fact that the high side power device requires an overvoltage driving signal at its gate of about 10 v. more than the motor voltage supply. If the motor voltage supply is, for example, 17 v., as the gate voltage rises to approximately 17 v., the output voltage also rises to about 17 v. When the gate voltage starts to ramp up from 17 v. to about 27 v., the high side op-amp pushes the gate to the charge pump voltage of 27 v. A problem arises, particularly when there is to be a transition or commutation from on to off and the drive is to be reduced with a fixed slew rate. At the beginning of such a transition, the gate is at the overvoltage of about 27 v. and the source of the power device is at about 17 v. It therefore takes time to discharge the gate down to 17 v. when the output can start reducing. Preslewing is a process to reduce that delay. To do so with past circuit designs for a good slew rate control requires elements occupying a very substantial chip area. It is desirable, at least for some drives, for the commutation to occur at least as fast as 15 v./microsecond. That would normally mean a huge P-channel device and a huge lateral N-channel DMOS structure in a current sinking path of a preslewing circuit. Huge, in this context, means about 400-600 microns for the channel width.
There is thus an unmet need in the art to be able to utilize a method for achieving effective slew rate control utilizing readily integrable elements by utilizing basic elements to achieve slew rate control in a circuit which is relatively easy to fabricate and which achieves a rapid turn-off of load current even when gate voltage of the output switching device is boosted with a separate voltage supply. Therefore, it would be advantageous in the art to be able to describe a method for overcoming the undesirable effects that occur when the gate voltage utilizes a separate boost supply and rapid load turn-off is required.